IDT82V3285AEQG【PDF 46/149 页】IC PLL WAN SE STRATUM 100TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录2000

42页 43页 44页 45页 [46页]47页 48页 49页 50页

IDT82V3285A

WAN PLL

Pin Description

August 7, 2009

IN4_POS

IN4_NEG

PECL/LVDS

IN4_POS / IN4_NEG: Positive / Negative Input Clock 4

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz

clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is

automatically detected.

Single-ended input for differential input is also supported. Refer to Chapter 9.3.2.3 Single-

Ended Input for Differential Input.

IN5

pull-down

CMOS

IN5: Input Clock 5

A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,

25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.

In Slave operation, the frequency of the T0 selected input clock IN5 is recommended to be

6.48 MHz.

Output Frame Synchronization Signal

FRSYNC_8K

CMOS

FRSYNC_8K: 8 kHz Frame Sync Output

An 8 kHz signal is output on this pin.

MFRSYNC_2K

CMOS

MFRSYNC_2K: 2 kHz Multiframe Sync Output

A 2 kHz signal is output on this pin.

Output Clock

OUT1

CMOS

OUT1: Output Clock 1

A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,

77.76 MHz or 155.52 MHz clock is output on this pin.

OUT2

CMOS

OUT2: Output Clock 2

A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,

77.76 MHz or 155.52 MHz clock is output on this pin.

OUT3

CMOS

OUT3: Output Clock 3

A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,

77.76 MHz or 155.52 MHz clock is output on this pin.

OUT4_POS

OUT4_NEG

PECL/LVDS

OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4

A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,

77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair

of pins.

OUT5_POS

OUT5_NEG

PECL/LVDS

OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5

A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,

5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,

77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair

of pins.

Microprocessor Interface

pull-up

CMOS

CS: Chip Selection

A transition from high to low must occur on this pin for each read or write operation and this

pin should remain low until the operation is over.

INT_REQ

CMOS

INT_REQ: Interrupt Request

This pin is used as an interrupt request. The output characteristics are determined by the

HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).

Table 1: Pin Description (Continued)

Name

Pin No.

I/O

Type

Description 1

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式